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1 features description applications tps720xx www.ti.com ........................................................................................................................................................ sbvs100d ? june 2008 ? revised august 2009 350ma, ultra-low v in , rf low-dropout linear regulator with bias pin 2 350ma high-performance ldo the tps720xx family of dual rail, low-dropout linear regulators (ldos) offers outstanding ac performance low quiescent current: 38 m a (psrr, load and line transient response), while excellent load transient response: consuming a very low quiescent current of 38 m a. 15mv for i load = 0ma to 350ma in 1 m s the v bias rail that powers the control circuit of the excellent line transient response: ldo draws very low current (on the order of the v out = 2mv for v bias = 600mv in 1 m s quiescent current of the ldo) and can be connected v out = 200 m v for v in = 400mv in 1 m s to any power supply that is equal to or greater than low noise: 48 m v rms (10hz to 100khz) 1.4v above the output voltage. the main power path is through v in , which can be a lower voltage than 80db v in psrr (10hz to 10khz) v bias ; it can be as low as v out + v do , increasing the 70db v bias psrr (10hz to 10khz) efficiency of the solution in many power-sensitive fast start-up time: 140 m s applications. for example, v in can be an output of a built-in soft-start with monotonic v out rise high-efficiency, dc-dc step-down regulator. and startup current limited to 100ma + i load the tps720xx supports a novel feature in which the over-current and thermal protection output of the ldo regulates under light loads when the in pin is left floating. the light-load drive current low dropout: 110mv at i load = 350ma is sourced from v bias under this condition. this stable with 2.2 m f output capacitor feature is particularly useful in power-saving available in 1,33mm x 0,96mm wcsp-5 and applications where the dc/dc converter connected to 2mm x 2mm son-6 packages the in pin is disabled but the ldo is still required to regulate the voltage to a light load. the tps720xx is stable with ceramic capacitors and digital cameras uses an advanced bicmos fabrication process that cellular camera phones yields a dropout of 110mv at a 350ma output load. the tps720xx has the unique feature of providing a wireless lan monotonic v out rise (overshoot limited to 3%) with handheld products v in inrush current limited to 100ma + i load with an output capacitor of 2.2 m f. the tps720xx uses a precision voltage reference and feedback loop to achieve overall accuracy of 2% over load, line, process, and temperature extremes. an ultra-small wafer chip-scale package (wcsp) makes the tps720xx ideal for handheld applications. the tps720xx is also available in a son-8 package. this family of devices is fully specified over the temperature range of t j = ? 40 c to +125 c. 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 all trademarks are the property of their respective owners. production data information is current as of publication date. copyright ? 2008 ? 2009, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters. biasin en gnd out c3 b2 a3 c1 a1 tps720xx yzu package 1,33mm x 0,96mm wcsp-5 (top view) ingnd bias 65 4 out nc en 12 3 thermal pad tps720xx drv package 2mm x 2mm son-6 (top view) tps720xx v en v batt inen out gnd v core 2.2 f ceramic m 1.3v 1.8v standalone dc/dc converter or pmu bias
absolute maximum ratings (1) dissipation ratings tps720xx sbvs100d ? june 2008 ? revised august 2009 ........................................................................................................................................................ www.ti.com this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ordering information (1) product v out (2) tps720 xxyyyz xx is nominal output voltage (for example, 28 = 2.8v, 285 = 2.85v). yyy is the package designator. z is tape and reel quantity (r = 3000, t = 250). (1) for the most current package and ordering information see the package option addendum at the end of this document, or see the ti website at www.ti.com . (2) output voltages from 0.9v to 3.6v in 50mv increments are available through the use of innovative factory eeprom programming; minimum order quantities may apply. contact factory for details and availability. at t j = ? 40 c to +125 c (unless otherwise noted). all voltages are with respect to gnd. parameter tps720xx unit input voltage range (steady-state), v in (2) ? 0.3 to v bias or +5.0 (3) v peak transient input voltage, v in_peak (4) +5.5 v bias voltage range, v bias ? 0.3 to +6.0 v enable voltage range, v en ? 0.3 to +6.0 v output voltage range, v out ? 0.3 to +5.0 v peak output current, i out internally limited output short-circuit duration indefinite total continuous power dissipation, p diss see dissipation ratings table human body model (hbm) 2000 v esd rating charged device model (cdm) 500 v machine model (mm) 100 v operating junction temperature range, t j ? 55 to +125 c storage temperature range, t stg ? 55 to +150 c (1) stresses above these ratings may cause permanent damage. exposure to absolute maximum conditions for extended periods may degrade device reliability. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. (2) to ensure proper operation of the device it is necessary that v in v bias under all conditions. (3) whichever is less. (4) for durations no longer than 1ms each, for a total of no more than 1000 occurrences over the lifetime of the device. derating factor board package r q jc r q ja above t a = +25 c t a < +25 c t a = +70 c t a = +85 c high-k (1) yzu 51 c/w 248 c/w 4mw/ c 403mw 222mw 160mw high-k (1) drv 20 c/w 65 c/w 15.4mw/ c 1580mw 845mw 615mw (1) the jedec high-k (2s2p) board used to derive this data was a 3- 3-inch, multilayer board with 1-ounce internal power and ground planes and 2-ounce copper traces on top and bottom of the board. 2 submit documentation feedback copyright ? 2008 ? 2009, texas instruments incorporated
electrical characteristics tps720xx www.ti.com ........................................................................................................................................................ sbvs100d ? june 2008 ? revised august 2009 over operating temperature range (t j = ? 40 c to +125 c), v bias = (v out + 1.4v) or 2.5v (whichever is greater); v in v out + 0.5v, i out = 1ma, v en = 1.1v, c out = 2.2 m f, unless otherwise noted. typical values are at t j = +25 c. parameter test conditions min typ max unit v bias or v in input voltage range 1.1 (1) v 4.5 (2) v bias bias voltage range 2.5 5.5 v output voltage range (4) 0.9 3.6 v nominal t j = +25 c ? 3.0 +3.0 mv v out + 1.4v v bias 5.5v, over v bias , v in , i out , v out + 0.5v v in 4.5v, ? 2.0 +2.0 % t j = ? 40 c to +125 c 0ma i out 350ma drv package only: v out + 1.4v v bias 5.5v, over v bias , v in , i out , v out + 0.5v v in 4.5v, ? 25 +25 mv t j = ? 40 c to +125 c v out (3) output 0ma i out 350ma, accuracy v out < 1.2v yzu package only: v out + 1.4v v bias 5.5v, over v bias , v in , i out , v out + 0.5v v in 4.5v, ? 1.0 +1.0 % t j = ? 10 c to +85 c 0ma i out 350ma 1.6v v out 3.3v v out + 1.4v v bias 5.5v, v in floating 1.0 % 0 m a i out 500 m a v out / v in v in line regulation v in = (v out + 0.5v) to 4.5v, i out = 1ma 16 m v/v v bias = (v out + 1.4v) or 2.5v (whichever is v out / v bias v bias line regulation 16 m v/v greater) to 5.5v, i out = 1ma v in line transient v in = 400mv, t rise = t fall = 1 m s 200 m v v bias line transient v bias = 600mv, t rise = t fall = 1 m s 0.8 mv v out / i out load regulation 0ma i out 350ma (no load to full load) ? 15 m v/ma load transient 0ma i out 350ma, t rise = t fall = 1 m s 15 mv v in = v out(nom) ? 0.1v, v do_in v in dropout voltage (5) (v bias ? v out(nom) ) = 1.4v, 110 200 mv i out = 350ma v do_bias v bias dropout voltage (6) v in = v out(nom) + 0.3v, i out = 350ma 1.09 1.4 v i cl output current limit v out = 0.9 v out(nom) 420 525 800 ma i out = 100 m a 38 m a i gnd ground pin current i out = 0ma to 350ma 54 80 m a i shdn shutdown current (i gnd ) v en 0.4v, t j = -40 c to +85 c 0.5 2 m a f = 10hz 85 db f = 100hz 85 db v in ? v out 0.5v, f = 1khz 85 db psrr v in power-supply rejection ratio v bias = v out + 1.4v, f = 10khz 80 db i out = 350ma f = 100khz 70 db f = 1mhz 50 db (1) performance specifications are ensured up to a minimum v in = v out + 0.5v. (2) whichever is less. (3) minimum v bias = (v out + 1.4v) or 2.5v (whichever is greater) and v in = v out + 0.5v. (4) v o nominal value is factory programmable through the onchip eeprom. (5) measured for devices with v out(nom) 1.2v. (6) v bias ? v out with v out = v out(nom) ? 0.1v. measured for devices with v out(nom) 1.8v. copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback 3
tps720xx sbvs100d ? june 2008 ? revised august 2009 ........................................................................................................................................................ www.ti.com electrical characteristics (continued) over operating temperature range (t j = ? 40 c to +125 c), v bias = (v out + 1.4v) or 2.5v (whichever is greater); v in v out + 0.5v, i out = 1ma, v en = 1.1v, c out = 2.2 m f, unless otherwise noted. typical values are at t j = +25 c. parameter test conditions min typ max unit f = 10hz 80 db f = 100hz 80 db v in ? v out 0.5v, f = 1khz 75 db psrr v bias power-supply rejection ratio v bias = v out + 1.4v, f = 10khz 65 db i out = 350ma f = 100khz 55 db f = 1mhz 35 db bw = 10hz to 100khz, v bias 2.5v, v n output noise voltage 48 m v rms v in = v out + 0.5v v bias = (v out +1.4v) or 2.5v (whichever is 100 + i vin_inrush inrush current on v in ma greater), v in = v out + 0.5v i load v out = 95% v out(nom) , i out = 350ma, t str startup time 140 m s c out = 2.2 m f v en(hi) enable pin high (enabled) 1.1 v v en(lo) enable pin low (disabled) 0 0.4 v i en enable pin current v en = 5.5v, v in = 4.5v, v bias = 5.5v 1.0 m a undervoltage lockout v bias rising 2.41 2.45 2.49 v uvlo hysteresis v bias falling 150 mv shutdown, temperature increasing +160 c t sd thermal shutdown temperature reset, temperature decreasing +140 c t j operating junction temperature ? 40 +125 c 4 submit documentation feedback copyright ? 2008 ? 2009, texas instruments incorporated
device information pin configuration tps720xx www.ti.com ........................................................................................................................................................ sbvs100d ? june 2008 ? revised august 2009 functional block diagram drv package yzu package son-6 wcsp-5 (top view) (top view) (1) it is recommended that the son (drv) package thermal pad be connected to ground. pin descriptions tps720xx name drv yzu description output pin. a 2.2 m f ceramic capacitor is connected from this pin to ground, for stability and to provide load out 1 a3 transients. see input and output capacitor requirements in the application information section. nc 2 ? no connection. enable pin. a logic high signal on this pin turns the device on and regulates the voltage from in to out. a en 3 c3 logic low on this pin turns off the device. bias supply pin. it is recommended that this input be bypassed with a ceramic capacitor to ground for better bias 4 c1 transient performance. see input and output capacitor requirements in the application information section. gnd 5 b2 ground pin. input pin. this pin can be a maximum of 4.5v; v in must not exceed v bias . bypass this input with a ceramic in 6 a1 capacitor to ground. see input and output capacitor requirements in the application information section. copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback 5 thermal shutdown current limit uvlo bandgap in en out bias ingnd bias 65 4 out nc en 12 3 thermal pad (1) bias in en gnd out c3 b2 a3 c1 a1
typical characteristics tps720xx sbvs100d ? june 2008 ? revised august 2009 ........................................................................................................................................................ www.ti.com over operating temperature range (t j = ? 40 c to +125 c), v bias = (v out + 1.4v) or 2.5v (whichever is greater); v in = v out + 0.5v, i out = 1ma, v en = 1.1v, c out = 2.2 m f, unless otherwise noted. typical values are at t j = +25 c. v in line regulation v in line regulation i out = 0ma (tps72013yzu) i out = 350ma (tps72013yzu) figure 1. figure 2. v bias line regulation v bias line regulation i out = 0ma (tps72013yzu) i out = 350ma (tps72013yzu) figure 3. figure 4. load regulation under light loads load regulation (tps72013yzu) (tps72013yzu) figure 5. figure 6. 6 submit documentation feedback copyright ? 2008 ? 2009, texas instruments incorporated 1.401.38 1.36 1.34 1.32 1.30 1.28 1.26 1.24 1.22 1.20 v (v) out 2.5 3.0 3.5 4.0 4.5 v (v) in +125 c +105 c +85 c - 10 c +25 c - 40 c 1.401.38 1.36 1.34 1.32 1.30 1.28 1.26 1.24 1.22 1.20 v (v) out 2.5 3.0 3.5 4.0 5.0 5.5 4.5 v (v) bias +125 c +105 c +85 c - 10 c +25 c - 40 c 1.401.38 1.36 1.34 1.32 1.30 1.28 1.26 1.24 1.22 1.20 v (v) out 2.5 3.0 3.5 4.0 5.0 5.5 4.5 v (v) bias +125 c +105 c +85 c - 10 c +25 c - 40 c 1.401.38 1.36 1.34 1.32 1.30 1.28 1.26 1.24 1.22 1.20 v (v) out 0 1 2 3 4 5 6 7 8 9 10 i (ma) out +125 c +105 c +85 c - 10 c +25 c - 40 c 1.401.38 1.36 1.34 1.32 1.30 1.28 1.26 1.24 1.22 1.20 v (v) out 0 50 100 150 200 250 300 350 i (ma) out +125 c +105 c +85 c - 10 c +25 c - 40 c 1.401.38 1.36 1.34 1.32 1.30 1.28 1.26 1.24 1.22 1.20 v (v) out 2.5 3.0 3.5 4.0 4.5 v (v) in +125 c +105 c +85 c - 10 c +25 c - 40 c
tps720xx www.ti.com ........................................................................................................................................................ sbvs100d ? june 2008 ? revised august 2009 typical characteristics (continued) over operating temperature range (t j = ? 40 c to +125 c), v bias = (v out + 1.4v) or 2.5v (whichever is greater); v in = v out + 0.5v, i out = 1ma, v en = 1.1v, c out = 2.2 m f, unless otherwise noted. typical values are at t j = +25 c. load regulation with v in floating load regulation with v in floating (tps72013yzu) (tps72013yzu) figure 7. figure 8. v in dropout voltage v bias dropout voltage vs output current (tps72013yzu) vs temperature (tps72033yzu) figure 9. figure 10. output voltage ground pin current vs temperature (tps72013yzu) vs v bias input voltage (tps72013yzu) figure 11. figure 12. copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback 7 1.401.38 1.36 1.34 1.32 1.30 1.28 1.26 1.24 1.22 1.20 v (ma) out 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 i (ma) out v = 2.7v bias v = 3.5v bias v = 4.5v bias v = 5.5v bias v = 3.0v bias v = 4.0v bias v = 5.0v bias t = +25 c j 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 i (ma) out 1.401.38 1.36 1.34 1.32 1.30 1.28 1.26 1.24 1.22 1.20 v (ma) ou t v = 2.7v bias t = 40 - j c t = +25 c j t = +85 c j t = +105 c j t = +125 c j t = 0 c j 160140 120 100 8060 40 20 0 v (mv) do_ in 0 50 100 150 200 250 300 350 i (ma) out +125 c +105 c +85 c - 10 c +25 c - 40 c 1.151.14 1.13 1.12 1.11 1.10 1.09 1.08 1.07 1.06 1.05 1.04 v = v - v do_ bias bi as ou t (v) - 40 - 25 - 10 125 95 80 65 50 20 35 5 110 t j (c) v = v - out out(nom) 0.1 i out = 350ma 1.3451.325 1.305 1.285 1.265 1.245 v (v) out - 40 - 25 - 10 125 95 80 65 50 20 35 5 110 t (c) j i = 350ma out i = 0ma out i = 1ma out 5045 40 35 30 25 20 15 10 50 i gnd ( m a) 2.5 3.0 3.5 4.0 5.0 5.5 4.5 v (v) bias +125 c i = 1ma out +105 c +85 c +25 c - 10 c - 40 c
tps720xx sbvs100d ? june 2008 ? revised august 2009 ........................................................................................................................................................ www.ti.com typical characteristics (continued) over operating temperature range (t j = ? 40 c to +125 c), v bias = (v out + 1.4v) or 2.5v (whichever is greater); v in = v out + 0.5v, i out = 1ma, v en = 1.1v, c out = 2.2 m f, unless otherwise noted. typical values are at t j = +25 c. ground pin current ground pin current vs output current (tps72013yzu) vs temperature (tps72013yzu) figure 13. figure 14. shutdown current current limit vs v bias input voltage (tps72013yzu) vs v bias input voltage (tps72013yzu) figure 15. figure 16. current limit v in power-supply ripple rejection vs v in input voltage (tps72013yzu) vs frequency (tps72015yzu) figure 17. figure 18. 8 submit documentation feedback copyright ? 2008 ? 2009, texas instruments incorporated 7060 50 40 30 20 10 0 i ( a) m gnd 0 50 100 150 200 250 300 350 i (ma) out +125 c +105 c +85 c - 10 c +25 c - 40 c 6050 40 30 20 10 0 i ( a) m gn d - 40 - 25 - 10 125 95 80 65 50 20 35 5 110 t ( c) j i = 350ma out 3.02.5 2.0 1.5 1.0 0.5 0 i shdn ( m a) 2.5 3.0 3.5 4.0 5.0 5.5 4.5 v (v) bias +125 c +105 c +85 c - 10 c +25 c - 40 c 675650 625 600 575 550 i (v) cl 2.5 3.0 3.5 4.0 5.0 5.5 4.5 v (v) bias +125 c - 10 c +25 c - 40 c +85 c +105 c 675650 625 600 575 550 i (ma) cl 2.5 3.0 3.5 4.0 4.5 v (v) in +125 c - 10 c +25 c - 40 c +85 c +105 c 120100 8060 40 20 0 psrr (db) 10 100 1k 1m 10k 100k 10m frequency (hz) i = 0ma out i = 350ma out i = 50ma out (v v - in out ) = 0.5v (v v - bias out ) = 1.4v
tps720xx www.ti.com ........................................................................................................................................................ sbvs100d ? june 2008 ? revised august 2009 typical characteristics (continued) over operating temperature range (t j = ? 40 c to +125 c), v bias = (v out + 1.4v) or 2.5v (whichever is greater); v in = v out + 0.5v, i out = 1ma, v en = 1.1v, c out = 2.2 m f, unless otherwise noted. typical values are at t j = +25 c. v in power-supply ripple rejection v bias power-supply ripple rejection vs frequency (tps72015yzu) vs frequency (tps72015yzu) figure 19. figure 20. output spectral noise density v in inrush current vs frequency (tps72015yzu) v in = 1.8v, v out = 1.3v, v bias = 2.7v, i out = 0ma figure 21. figure 22. v in line transient response v in inrush current v in = 1.6v to 2.0v, v out = 1.3v, v bias = 2.7v, v in = 1.8v, v out = 1.3v, v bias = 2.7v, i out = 350ma v in slew rate = 1v/ m s, i out = 350ma figure 23. figure 24. copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback 9 100 8060 40 20 0 psrr (db) 10 100 1k 1m 10k 100k 10m frequency (hz) i = 350ma out (v v - in out ) = 350mv (v v in out - ) = 300mv (v v in out - ) = 250mv 100 8060 40 20 0 psrr (db) 10 100 1k 1m 10k 100k 10m frequency (hz) i = 1ma out i = 350ma out (v v in out - ) = 0.5v (v v bias out - ) = 1.4v 500mv/div v out i in en 50ma/div 200mv/div 20 s/div m v = 1.3v out i = 110ma in-peak 10 1 0.1 0.01 output spectral noise density ( m v/ ? ) hz 100 1k 10k 100k frequency (hz) 1mv/div v out v in 200mv/div 100 s/div m 1.6v 2.0v 500mv/div v out i in en 200ma/div200mv/div 20 s/div m v = 1.3v out i = 400ma in-peak
tps720xx sbvs100d ? june 2008 ? revised august 2009 ........................................................................................................................................................ www.ti.com typical characteristics (continued) over operating temperature range (t j = ? 40 c to +125 c), v bias = (v out + 1.4v) or 2.5v (whichever is greater); v in = v out + 0.5v, i out = 1ma, v en = 1.1v, c out = 2.2 m f, unless otherwise noted. typical values are at t j = +25 c. v bias line transient response v in = 1.8v, v out = 1.3v, v bias = 2.7v to 3.3v, load transient response v bias slew rate = 600m/ m s, i out = 350ma v in = 1.8v, v out = 1.3v, v bias = 2.7v, t rise = 1 m s figure 25. figure 26. 10 submit documentation feedback copyright ? 2008 ? 2009, texas instruments incorporated 1mv/div v out v bias 200mv/div 100 s/div m 2.7v 3.3v 10mv/div v out i out 100ma/div 100 s/div m 0ma 300ma
application information internal current limit input and output capacitor inrush current limit board layout recommendations to tps720xx www.ti.com ........................................................................................................................................................ sbvs100d ? june 2008 ? revised august 2009 ground connection for the output capacitor should be the tps720xx belongs to a family of new generation connected directly to the gnd pin of the device. high ldo regulators that use innovative circuitry to equivalent series resistance (esr) capacitors may achieve ultra-wide bandwidth and high loop gain, degrade psrr. the bias pin draws very little current resulting in extremely high psrr (up to 1mhz) at and can be routed as a signal (make sure to shield it very low headroom (v in ? v out ). the implementation from high-frequency coupling). of the bias pin on the tps720xx vastly improves efficiency of low v out applications by allowing the use of a preregulated, low-voltage input supply. the tps720xx supports a novel feature in which the the tps720xx internal current limits help protect the output of the ldo regulates under light loads regulator during fault conditions. during current limit, ( < 500 m a) when the in pin is left floating. the the output sources a fixed amount of current that is light-load drive current is sourced from v bias under largely independent of output voltage. in such a case, this condition. this feature is particularly useful in the output voltage is not regulated, and is power-saving applications where the dc/dc converter v out = i limit r load . the nmos pass transistor connected to the in pin is disabled but the ldo is still dissipates (v in ? v out ) i limit until thermal shut down required to regulate the voltage to a light load. these is triggered and the device is turned off. as the features, combined with low noise, low ground pin device cools down, it is turned on by the internal current, and ultra-small packaging, make this device thermal shutdown circuit. if the fault condition ideal for portable applications. this family of continues, the device cycles between current limit regulators offers sub-bandgap output voltages, and thermal shutdown. see the thermal information current limit and thermal protection, and is fully section for more details. specified from ? 40 c to +125 c. the nmos pass element in the tps720xx has a built-in body diode that conducts current when the voltage at out exceeds the voltage at in. this requirements current is not limited, so if extended reverse voltage although an input capacitor is not required for stability operation is anticipated, external limiting to 5% of on the in pin, it is good analog design practice to rated output current is recommended. connect a 0.1 m f to 1.0 m f low equivalent series resistance (esr) capacitor across the in pin input supply near the regulator. this capacitor counteracts the tps720xx family of ldo regulators implement a reactive input sources and improves transient novel inrush current-limit circuit architecture: the response, noise rejection, and ripple rejection. a current drawn through the in pin is limited to a finite higher-value capacitor may be necessary if large, fast value. this i inrushlimit charges the output to its final rise-time load transients are anticipated, or if the voltage. all the current drawn through v in goes to device is located close to the power source. if source charge the output capacitance when the load is impedance is not sufficiently low, a 0.1 m f input disconnected. the following equation shows the capacitor may be necessary to ensure stability. inrush current limit performed by the circuit: the bias pin does not require an input capacitor i inrushlimit (a) = c out ( m f) 0.0454545(v/ m s) + because it does not source high currents. however, if i load (a) (1) source impedance is not sufficiently low, a small 0.1 m f bypass capacitor is recommended. assuming a c out of 2.2 m f with the load disconnected (that is, i load = 0) the i inrushlimit is calculated to be the tps720xx is designed to be stable with standard 100ma. the inrush current charges the ldo output ceramic capacitors with values of 2.2 m f or larger at capacitor. if the output of the ldo regulates to 1.3v, the output. x5r- and x7r-type capacitors are best then the ldo charges the output capacitor to the final because they have minimal variation in value and output value in approximately 28.6 m s. esr over temperature. maximum esr should be less than 250m ? . another consideration is when a load is connected to the output of an ldo. the connected load tries to steer a portion of the current away from v out . the tps720xx inrush current-limit circuit employs a new improve psrr and noise performance technique that supplies not only the i inrushlimit , but to improve ac performance such as psrr, output also the additional current needed by the load. if noise, and transient response, it is recommended that i load = 350ma, then the i inrushlimit calculates to be the board be designed with separate ground planes approximately 450ma (from equation 1 ). for v in and v out , with the ground plane connected only at the gnd pin of the device. in addition, the copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback 11
shutdown minimum load dropout voltage output regulation with in pin transient response undervoltage lock-out (uvlo) tps720xx sbvs100d ? june 2008 ? revised august 2009 ........................................................................................................................................................ www.ti.com the enable pin (en) is active high and is compatible the tps720xx is stable with no output load. with standard and low voltage, ttl-cmos levels. traditional ldos suffer from low loop gain at very when shutdown capability is not required, en can be light output loads. the tps720xx employs an connected to the in pin. innovative, low-current mode circuit under very light or no-load conditions, resulting in improved output voltage regulation performance down to zero output current. the tps720xx uses a nmos pass transistor to achieve low dropout. when (v in ? v out ) is less than the dropout voltage (v do ), the nmos pass device is floating in the linear region of operation and the input-to-output resistance is the r ds(on) of the nmos the tps720xx supports a novel feature in which the pass element. v do approximately scales with output output of the ldo regulates under light loads when current because the nmos device behaves as a the in pin is left floating. under normal conditions, resistor in dropout. when the in pin is connected to a power source, the bias pin draws only tens of milliamperes. however, as with any linear regulator, psrr and transient when the in pin is floating, an innovative circuit is response are degraded as (v in ? v out ) approaches used that allows a mximum current of 500 m a to be dropout. this effect is shown in figure 19 in the drawn by the load through the bias pin, while typical characteristics section. maintaining the output in regulation. this feature is particularly useful in power-saving applications where a dc/dc converter connected to the in pin is disabled, but the ldo is required to regulate the output voltage as with any regulator, increasing the size of the to a light load. output capacitor reduces over/undershoot magnitude but increases duration of the transient response. figure 27 shows an application example where a microcontroller is not turned off (to maintain the state of the internal memory), but where the regulated supply (shown as the tps62xxx) is turned off to the tps720xx uses an undervoltage lock-out circuit reduce power. in this case, the tps720xx bias pin on the bias pin to keep the output shut off until the provides sufficient load current to maintain a internal circuitry is operating properly. the uvlo regulated voltage to the microcontroller. circuit has a deglitch feature so that it typically ignores undershoot transients on the input if they are less than 50 m s duration. figure 27. example of floating in pin regulation 12 submit documentation feedback copyright ? 2008 ? 2009, texas instruments incorporated microcontroller tps720xx tps62xxx vin en sw fb in out bias en gnd 2.2 m f 10 m f 10 m h 2.5v to 5.5v control to turn on/off the dc/dc output of dc/dc is floating whenthe tps62xxx en pin is low gnd
thermal information power dissipation package mounting tps720xx www.ti.com ........................................................................................................................................................ sbvs100d ? june 2008 ? revised august 2009 thermal protection disables the output when the the ability to remove heat from the die is different for junction temperature rises to approximately +160 c, each package type, presenting different allowing the device to cool. when the junction considerations in the printed circuit board (pcb) temperature cools to approximately +140 c, the layout. the pcb area around the device that is free output circuitry is again enabled. depending on power of other components moves the heat from the device dissipation, thermal resistance, and ambient to the ambient air. performance data for jedec low- temperature, the thermal protection circuit may cycle and high-k boards are given in the dissipation on and off. this cycling limits the dissipation of the ratings table. using heavier copper increases the regulator, protecting it from damage as a result of effectiveness in removing heat from the device. the overheating. addition of plated through-holes to heat-dissipating layers also improves the heatsink effectiveness. any tendency to activate the thermal protection circuit indicates excessive power dissipation or an power dissipation depends on input voltage and load inadequate heatsink. for reliable operation, junction conditions. power dissipation (p d ) is equal to the temperature should be limited to +125 c maximum. product of the output current times the voltage drop to estimate the margin of safety in a complete design across the output pass element (v in to v out ), as (including heatsink), increase the ambient shown in equation 2 : temperature until the thermal protection is triggered; p d = (v in ? v out ) i out (2) use worst-case loads and signal conditions. for good reliability, thermal protection should trigger at least +35 c above the maximum expected ambient condition of the particular application. this solder pad footprint recommendations for the configuration produces a worst-case junction tps720xx are available from the texas instruments temperature of +125 c at the highest expected web site at www.ti.com . ambient temperature and worst-case load. the internal protection circuitry of the tps720xx has been designed to protect against overload conditions. it was not intended to replace proper heatsinking. continuously running the tps720xx into thermal shutdown degrades device reliability. figure 28. yzu wafer chip-scale package dimensions (in mm) copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback 13 n tes: o 1,3621,302 1. all linear dimen eters. sions are in millim 2. this drawing is sub out notice. ject to change with 0,9940,934
tps720xx sbvs100d ? june 2008 ? revised august 2009 ........................................................................................................................................................ www.ti.com revision history note: page numbers for previous revisions may differ from page numbers in the current version. changes from revision c (september, 2008) to revision d ......................................................................................... page added electrical specifications for drv package .................................................................................................................. 3 noted electrical specifications for yzu package ................................................................................................................... 3 14 submit documentation feedback copyright ? 2008 ? 2009, texas instruments incorporated
package option addendum www.ti.com 11-apr-2013 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) op temp (c) top-side markings (4) samples TPS72009YZUR active dsbga yzu 5 3000 green (rohs & no sb/br) snagcu level-1-260c-unlim -40 to 125 g3 tps72009yzut active dsbga yzu 5 250 green (rohs & no sb/br) snagcu level-1-260c-unlim -40 to 125 g3 tps720105drvr active son drv 6 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 odc tps720105drvt active son drv 6 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 odc tps720105yzur active dsbga yzu 5 3000 green (rohs & no sb/br) snagcu level-1-260c-unlim -40 to 125 nm tps720105yzut active dsbga yzu 5 250 green (rohs & no sb/br) snagcu level-1-260c-unlim -40 to 125 nm tps72010drvr active son drv 6 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 daa tps72010drvt active son drv 6 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 daa tps720115drvr active son drv 6 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 shp tps720115drvt active son drv 6 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 shp tps72011drvr active son drv 6 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 par tps72011drvt active son drv 6 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 par tps72011yzur active dsbga yzu 5 3000 green (rohs & no sb/br) snagcu level-1-260c-unlim -40 to 125 bq tps72011yzut active dsbga yzu 5 250 green (rohs & no sb/br) snagcu level-1-260c-unlim -40 to 125 bq tps72012drvr active son drv 6 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 dab tps72012drvt active son drv 6 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 dab tps72012yzur active dsbga yzu 5 3000 green (rohs & no sb/br) snagcu level-1-260c-unlim -40 to 125 nn
package option addendum www.ti.com 11-apr-2013 addendum-page 2 orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) op temp (c) top-side markings (4) samples tps72012yzut active dsbga yzu 5 250 green (rohs & no sb/br) snagcu level-1-260c-unlim -40 to 125 nn tps72013yzur active dsbga yzu 5 3000 green (rohs & no sb/br) snagcu level-1-260c-unlim -40 to 125 fs tps72013yzut active dsbga yzu 5 250 green (rohs & no sb/br) snagcu level-1-260c-unlim -40 to 125 fs tps72015drvr active son drv 6 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 dac tps72015drvt active son drv 6 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 dac tps72015yzur active dsbga yzu 5 3000 green (rohs & no sb/br) snagcu level-1-260c-unlim -40 to 125 ft tps72015yzut active dsbga yzu 5 250 green (rohs & no sb/br) snagcu level-1-260c-unlim -40 to 125 ft tps72017yzur active dsbga yzu 5 3000 green (rohs & no sb/br) snagcu level-1-260c-unlim -40 to 125 gc tps72017yzut active dsbga yzu 5 250 green (rohs & no sb/br) snagcu level-1-260c-unlim -40 to 125 gc tps72018drvr active son drv 6 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 dad tps72018drvt active son drv 6 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 dad tps72018yzur active dsbga yzu 5 3000 green (rohs & no sb/br) snagcu level-1-260c-unlim -40 to 125 gd tps72018yzut active dsbga yzu 5 250 green (rohs & no sb/br) snagcu level-1-260c-unlim -40 to 125 gd (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined.
package option addendum www.ti.com 11-apr-2013 addendum-page 3 pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) multiple top-side markings will be inside parentheses. only one top-side marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire top-side marking for that device. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant TPS72009YZUR dsbga yzu 5 3000 180.0 8.4 1.07 1.42 0.74 4.0 8.0 q1 tps72009yzut dsbga yzu 5 250 180.0 8.4 1.07 1.42 0.74 4.0 8.0 q1 tps720105drvr son drv 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 q2 tps720105drvr son drv 6 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 q2 tps720105drvt son drv 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 q2 tps720105drvt son drv 6 250 180.0 8.4 2.3 2.3 1.15 4.0 8.0 q2 tps720105yzur dsbga yzu 5 3000 180.0 8.4 1.07 1.42 0.74 4.0 8.0 q1 tps720105yzut dsbga yzu 5 250 180.0 8.4 1.07 1.42 0.74 4.0 8.0 q1 tps72010drvr son drv 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 q2 tps72010drvt son drv 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 q2 tps720115drvr son drv 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 q2 tps720115drvt son drv 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 q2 tps72011drvr son drv 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 q2 tps72011drvt son drv 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 q2 tps72011yzur dsbga yzu 5 3000 180.0 8.4 1.07 1.42 0.74 4.0 8.0 q1 tps72011yzut dsbga yzu 5 250 180.0 8.4 1.07 1.42 0.74 4.0 8.0 q1 tps72012drvr son drv 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 q2 tps72012drvt son drv 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 q2 package materials information www.ti.com 7-sep-2013 pack materials-page 1
device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant tps72012yzur dsbga yzu 5 3000 180.0 8.4 1.07 1.42 0.74 4.0 8.0 q1 tps72012yzut dsbga yzu 5 250 180.0 8.4 1.07 1.42 0.74 4.0 8.0 q1 tps72013yzur dsbga yzu 5 3000 180.0 8.4 1.07 1.42 0.74 4.0 8.0 q1 tps72013yzut dsbga yzu 5 250 180.0 8.4 1.07 1.42 0.74 4.0 8.0 q1 tps72015drvr son drv 6 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 q2 tps72015drvr son drv 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 q2 tps72015drvt son drv 6 250 180.0 8.4 2.3 2.3 1.15 4.0 8.0 q2 tps72015drvt son drv 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 q2 tps72015yzur dsbga yzu 5 3000 180.0 8.4 1.07 1.42 0.74 4.0 8.0 q1 tps72015yzut dsbga yzu 5 250 180.0 8.4 1.07 1.42 0.74 4.0 8.0 q1 tps72017yzur dsbga yzu 5 3000 180.0 8.4 1.07 1.42 0.74 4.0 8.0 q1 tps72017yzut dsbga yzu 5 250 180.0 8.4 1.07 1.42 0.74 4.0 8.0 q1 tps72018drvr son drv 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 q2 tps72018drvt son drv 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 q2 tps72018yzur dsbga yzu 5 3000 180.0 8.4 1.07 1.42 0.74 4.0 8.0 q1 tps72018yzut dsbga yzu 5 250 180.0 8.4 1.07 1.42 0.74 4.0 8.0 q1 *all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) TPS72009YZUR dsbga yzu 5 3000 182.0 182.0 17.0 package materials information www.ti.com 7-sep-2013 pack materials-page 2
device package type package drawing pins spq length (mm) width (mm) height (mm) tps72009yzut dsbga yzu 5 250 182.0 182.0 17.0 tps720105drvr son drv 6 3000 203.0 203.0 35.0 tps720105drvr son drv 6 3000 210.0 185.0 35.0 tps720105drvt son drv 6 250 203.0 203.0 35.0 tps720105drvt son drv 6 250 210.0 185.0 35.0 tps720105yzur dsbga yzu 5 3000 210.0 185.0 35.0 tps720105yzut dsbga yzu 5 250 210.0 185.0 35.0 tps72010drvr son drv 6 3000 203.0 203.0 35.0 tps72010drvt son drv 6 250 203.0 203.0 35.0 tps720115drvr son drv 6 3000 203.0 203.0 35.0 tps720115drvt son drv 6 250 203.0 203.0 35.0 tps72011drvr son drv 6 3000 203.0 203.0 35.0 tps72011drvt son drv 6 250 203.0 203.0 35.0 tps72011yzur dsbga yzu 5 3000 182.0 182.0 17.0 tps72011yzut dsbga yzu 5 250 182.0 182.0 17.0 tps72012drvr son drv 6 3000 203.0 203.0 35.0 tps72012drvt son drv 6 250 203.0 203.0 35.0 tps72012yzur dsbga yzu 5 3000 210.0 185.0 35.0 tps72012yzut dsbga yzu 5 250 210.0 185.0 35.0 tps72013yzur dsbga yzu 5 3000 210.0 185.0 35.0 tps72013yzut dsbga yzu 5 250 210.0 185.0 35.0 tps72015drvr son drv 6 3000 210.0 185.0 35.0 tps72015drvr son drv 6 3000 203.0 203.0 35.0 tps72015drvt son drv 6 250 210.0 185.0 35.0 tps72015drvt son drv 6 250 203.0 203.0 35.0 tps72015yzur dsbga yzu 5 3000 210.0 185.0 35.0 tps72015yzut dsbga yzu 5 250 210.0 185.0 35.0 tps72017yzur dsbga yzu 5 3000 210.0 185.0 35.0 tps72017yzut dsbga yzu 5 250 210.0 185.0 35.0 tps72018drvr son drv 6 3000 203.0 203.0 35.0 tps72018drvt son drv 6 250 203.0 203.0 35.0 tps72018yzur dsbga yzu 5 3000 210.0 185.0 35.0 tps72018yzut dsbga yzu 5 250 210.0 185.0 35.0 package materials information www.ti.com 7-sep-2013 pack materials-page 3

d: max = e: max = 1.362 mm, min = 0.994 mm, min = 1.302 mm0.934 mm
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